Embodiments of the present invention relate to a semiconductor device and a method for operating the same.
A flash memory device is a type of electrically erasable and programmable read-only memory (EEPROM) in which multiple memory regions can be erased or programmed by a single program action.
A system including a flash memory device can operate more quickly and more effectively than a system which simultaneously reads data from and writes data in other memory devices. All types of flash memory devices include cells that wear out after a predetermined number of erasing operations. This is because since an insulation film enclosing a charge storage element of a cell, which is configured to store data, is damaged by the erasing operations.
A flash memory device is designed to retain data stored therein even when not powered. That is, a flash memory device can retain the stored data without power consumption.
In addition, a flash memory device has excellent resistance to physical impact and a very high read access speed. As a result, flash memory devices have been widely used as storage devices in mobile products using battery power.
Flash memory devices are classified as NOR flash memory devices or NAND flash memory devices depending on the type of logic gates used in a storage unit of the flash memory devices.
A flash memory device is configured to store data in an array of transistors called cells. Flash memory devices may include a single-level cell or a multi-level cell. In a single-level cell device, a cell stores 1-bit data. In a multi-level cell device, a cell stores two or more bit data by changing the amount of charges on a floating gate of the cell.
In a flash memory device employing a floating gate, data retention characteristics and the number (or durability) of programming/erasing cycles are very important factors in determining the reliability of the flash memory device.
Charges (or electrons) stored in a cell of the flash memory device may leak from a floating gate through various failure mechanisms, for example, thermion emission and charge diffusion through a defective inter-poly insulation film, ion impurities, program disturbance stress, etc., resulting in reduction of a threshold voltage.
As the floating gate slowly accumulates charges while a power-supply voltage is applied to a control gate of the cell, an effect against charge acquisition may occur, resulting in an increased threshold voltage.
Repeated programming/erasing cycles may cause stress in oxide films of transistors in the flash memory device. Due to this stress, a failure may occur, such as a breakdown of a tunnel oxide film in the flash memory device.
A threshold voltage of a memory cell may gradually decrease due to the occurrence of such stress. In other words, electrons may leak from a floating gate of a programmed memory cell.
In sum, threshold voltage distribution of programmed memory cells moves to a lower voltage, such that some memory cells may have a threshold voltage lower than a program verification voltage. The reduction of the threshold voltage reduces a sensing margin in a read operation, and thus a read failure may occur.
Although a memory cell of a conventional memory device has non-volatile characteristics, cell data deterioration may occur over time under ordinary conditions. As a result, a data retention time is limited, and it is difficult to maintain the non-volatile characteristics, even under optimal conditions, for a long period of time.
If data stored in a non-volatile memory device is affected by deteriorated data retention characteristics, charge movement may occur over time, and thus a sensing margin of the data may be reduced. In this case, data necessary for controlling internal operations of the non-volatile memory device and stored in the non-volatile memory device may also change. Thereafter, a malfunction may occur when the non-volatile memory device operates in response to a user input.